The present invention relates to a thin film transistor (TFT) that is used in liquid crystal display (LCD), organic light emitting diode (OLED) and 3-D integrated semiconductor device or the like, and more particularly to a method for crystallizing an active layer forming the source, drain and channel regions of a thin film transistor using crystal filtering technique.
According to the present invention, the active layer of a thin film transistor can be crystallized into single crystalline silicon by filtering a crystal component having a uniform crystal orientation from a poly-crystal region which is crystallized by metal induced lateral crystallization (MILC) caused by MIC source metal.
Generally, the amorphous silicon transistor used in display devices such as LCD and OLED is fabricated by forming a gate electrode on a transparent substrate of glass or quartz, depositing gate oxide film, depositing amorphous silicon and n-type amorphous silicon, forming source and drain regions, and then forming an insulating layer. Generally, the active layer constituting the source, drain and channel regions of a thin film transistor is formed on a substrate such as glass or quartz using chemical vapor deposition (CVD) method. Since the active layer formed by CVD is made of amorphous silicon, it has low electron mobility of 1 cm2/Vs or less. As the size of LCD using TFT is being miniaturized and its aperture ratio is being reduced, a technique that may simultaneously form the drive IC and the pixel transistor has been required. In order to do so, a technique of crystallizing an amorphous silicon layer into a poly-crystal silicon layer with thermal treatment is used.
A poly-crystal silicon layer transistor is formed by first depositing an amorphous silicon layer on a substrate of glass or quartz and the like, poly-crystallizing the silicon layer and forming a gate oxide film and a gate electrode, implanting dopant in the source and drain, activating the dopant through annealing, and finally forming an insulating layer. Generally, the electron mobility of poly-crystal silicon layer is in the range of xcx9c100 cm2/Vs. Thus, using the poly-crystal silicon, the drive IC of LCD may be integrated into the same substrate with the pixel transistors. The important factors that determine the characteristics of a poly-crystal TFT are the number and configuration of the crystal grains boundaries existing in the poly-crystal silicon. According to the number and configuration of the grain crystal boundaries in the poly-crystal silicon, the electron mobility and the threshold voltage of the poly-crystal thin film transistor vary significantly.
As a poly-crystal thin film transistor inevitably includes crystal grain boundaries in its active layer made of poly-crystal silicon, it has lower electron mobility as compared to the electron mobility of 800 cm2/Vs of single crystalline silicon and higher degree of device non-uniformity. When fabricating a LCD using poly-crystal silicon layer transistors, the drive IC and the pixel transistor may be formed on the same substrate. However, due to the electron mobility of the poly-crystal silicon which is much lower than that of single crystal silicon, active elements such as the LCD controller, DAC, clock generator or the like may not be formed on the substrate. Also the increased device non-uniformity causes the deterioration of the display quality and the decreases of the productivity. Therefore, in order to secure uniform device characteristics equivalent to a single crystalline silicon device, some techniques for forming a single crystalline silicon layer with an amorphous silicon layer have been used.
A variety of methods for fabricating single crystalline silicon transistor have been proposed. Sequential lateral solidification (SLS) is a technique that forms single crystalline silicon in a local region while crystallizing an amorphous silicon layer by laser scanning using Chevron-type masks. The SLS method has a technical problem in precisely controlling the scanning of the laser beam. The method also has a limitation in obtaining single crystalline thin film having uniform characteristics because the crystal grains in the poly-crystal silicon frequently infiltrates into the locally formed single crystal silicon region. Also, as this method may process only one substrate at a time, the productivity of the process is lower than that of the batch process using a furnace.
Continuous grain solidification (CGS) is a technique that obtains crystallized silicon layer having substantially uniform crystal orientation by contacting or implanting metal such as nickel, palladium, aluminum and the like in amorphous silicon and crystallizing the amorphous silicon at a low temperature of 200xcx9c500xc2x0 C. The CGS method has a disadvantage of requiring a gettering process, which involves an additional thermal treatment to remove the silicide component used as a catalyst for crystallizing the amorphous silicon. And, as the silicon layer formed by the CGS method is not essentially single crystalline, its electrical characteristics are inferior to those of a single crystal silicon film.
Recently, a method for crystallizing a silicon layer by using metal induced lateral crystallization (MILC) phenomenon was proposed. (See S. W. Lee et al., IEEE Electron Device Letter, 17(4), p.160, 1996) The MILC phenomenon induces successive crystallization of amorphous silicon layer as the silicide produced by the reaction of the metal and the amorphous silicon propagates in the lateral direction of the silicon layer. When the MILC method is used, as the metal component used to crystallize the amorphous silicon does not remain in the crystallized region, it avoids the problem that the metal component remaining in the crystallized silicon region causes leakage current and deteriorates other electrical characteristics. Also, when using the MILC method, as the crystallization of silicon layer is induced at relatively low temperature of 300xcx9c500xc2x0 C., a plurality of substrates may be simultaneously crystallized in a furnace without causing damages to the substrates.
FIG. 1a to FIG. 1d are cross-sectional views illustrating the process of prior art for crystallizing a silicon layer constituting the active layer of a thin film transistor using MIC and MILC.
Referring to FIG. 1a, an amorphous silicon layer 10 is deposited on an insulating substrate 100 on which a buffer layer (not illustrated) is formed. Then the amorphous silicon layer 10 is patterned to form an active layer. A gate insulating layer 11 and a gate electrode 12 are formed on the active layer using conventional methods. As shown in FIG. 1b, a source region 10S and a drain region 10D are respectively formed in the active layer by doping impurity into the whole substrate using the gate electrode as a mask. As shown in FIG. 1c, photoresist 13 is formed to cover the gate electrode and the source and drain regions adjacent the gate electrode 12 and then a metal layer 14 is deposited on the entire surface of the photoresist 13 and the substrate. It is desirable that the metal layer is formed by depositing Ni at a thickness of about 20 xc3x85. As shown in FIG. 1d, when performing thermal treatment of the entire substrate at temperature of 300xc2x0 C. to 500xc2x0 C. after removing the photoresist, the source and drain regions below the metal layer remaining after the removal of the photoresist is crystallized by metal induced crystallization (MIC) that directly crystallizes the silicon by the MIC source metal which is in contact with or implanted in the amorphous silicon. And the amorphous silicon in the metal offset region and in the channel region 10C beneath the gate electrode is crystallized by the MILC that propagates from the MIC region. As shown in FIG. 1a to FIG. 1d, the photoresist is formed to cover portions of the source and the drain regions on both sides of the gate electrode 12. It is because, if the metal layer 14 is deposited up to boundaries between the channel region and the source/drain regions, the metal component introduced into and remaining in the channel boundaries and in the channel region during the MIC adversely affects the operation characteristics and leakage current of the channel region.
As the operation of the source and the drain regions (except for the channel region) is not critically affected by the residual metal component, the source and the drain regions apart from the channel region over 0.01-5 xcexcm are crystallized by the MIC and only the channel region and its peripheral regions are crystallized by the MILC. As a result, the time for crystallizing the entire amorphous silicon layer may be reduced.
FIG. 2a and FIG. 2b are electron microscope photographs of the crystalline structures of the silicon layer formed by conventional MIC and MILC methods. And FIG. 2c is a schematic diagram illustrating the crystallization state of the silicon layer in the photographs. The MIC region in which the metal catalyst exists is crystallized into polycrystal silicon. And the MILC region is crystallized to form poly-crystal silicon including several crystal grain boundaries as shown in FIG. 2c. Meanwhile, as shown in FIG. 2b, the poly-crystal silicon region being crystallized by the MILC comprises a few crystal grains growing into the same direction. As the crystallized silicon layer constituting an active layer with a typical size of 2xcx9c20 xcexcm generally includes one or more crystal grain boundaries, the electron mobility and the uniformity of the silicon layer are deteriorated. Therefore, in order to improve the performance of the thin film transistor including a poly-crystal active layer crystallized by MILC, a technique for crystallizing amorphous silicon into single crystalline silicon using MILC has been required.
To overcome the problems of the poly-crystal silicon produced by the conventional MILC method, the present invention provides a method for crystallizing amorphous silicon directly into single crystalline silicon using the MILC method. Specifically, the present invention provides a method for single-crystallizing amorphous silicon at a relatively low temperature by applying a crystal filtering technique to the MILC method.
In order to achieve these objects, the present invention forms a crystal seed at a desired region of a silicon layer on a substrate utilizing the MIC method, and grows crystal grains from the MIC crystal seed in the lateral direction utilizing the MILC method. Then the present invention filters the crystal grains being grown by the MILC and let some or one of the crystal grains continue to grow in the amorphous silicon region beyond the crystal filtering area. Thus, the amorphous silicon region beyond the crystal filtering area may be crystallized into single crystalline silicon as the filtered crystal grain (or grains) grows in the region by the MILC. Herein, the growth temperature of the crystal grain is typically limited to 650xc2x0 C. or less to prevent the growth or generation of crystal grains outside of the MILC region being crystallized by the MILC. According to the present invention, a single crystalline silicon layer extending to tens to hundreds of xcexcm may be obtained and the silicon layer thus obtained may be used to fabricate a semiconductor device such as TFT.
The present invention uses MIC source metal such as Ni to lower the crystallization temperature of amorphous silicon. In this connection, the present invention has an object to prevent the MIC source metal from affecting the performance of the semiconductor device by forming the single crystalline layer not in the MIC region where the MIC source metal resides but in the MILC region free of the MIC source metal. Also, the object of the present invention is to provide a thin film transistor comprising single crystalline silicon layer fabricated by the low-temperature crystallization method.
The present invention performs the crystallization of amorphous silicon layer at a temperature of 650xc2x0 C. or less which is lower than the transformation temperature of glass. Thus, the method of the present invention may be used to fabricate semiconductor devices such as TFT on a substrate made of glass. Also, using the present invention, thin film transistors constituting the switching and driving elements of display devices such as LCD and OLED may be directly formed on the substrate.
FIG. 3a to FIG. 3c and FIG. 4a to FIG. 4c show the process of single-crystallizing amorphous silicon layer by the MILC utilizing the crystal filtering technique. FIG. 3a to FIG. 3c show the crystallization of amorphous silicon by the MILC propagating from the right side to left side in the drawing, in which Ni is used as the MIC source metal. Herein, FIG. 3a is a dark image of an optical microscope taken after thermal treatment of amorphous silicon for 30 hours at the temperature of 520xc2x0 C.
As shown in the photograph, the crystallization by MILC is progressed in the right side of the filter channel 32 and poly-crystal silicon region 31 is formed therein. And the MILC is also progressed in the left side of the filter channel to create a single-crystal silicon region 33 rather than a poly-crystal silicon region. As shown in FIG. 2b and FIG. 2c, needle-shaped single crystal grains grow in the crystal growth front of the region poly-crystallized by MILC. If these needle-shaped single crystal grains continuously grow in irregular orientations, poly-crystal silicon is eventually formed in the MILC region. As shown in FIG. 3a, if the width of the filter channel 32 is adjusted so that only one crystal grain formed in the poly-crystal silicon region 31 may pass, the crystal grain passed the filter channel continue to grow so that it crystallizes the left side of the channel region into single-crystal silicon.
The single crystal passing the filter channel may grow up to hundreds of xcexcm or more, and FIG. 4a to FIG. 4c show the crystallization state changed after performing additional thermal treatment for 15 hours to the structure of FIG. 3a to FIG. 3c. The region 34 where Ni was formed as the MIC source metal is shown in the right side of the drawings. The amorphous silicon in the MILC region 33 in FIG. 3 in the left side of the filter channel 32 is completely single-crystallized in FIGS. 4a to 4c, and the growth of the single crystal in the left side of the filer channel reaches hundreds of xcexcm or more. As the typical size of the active layer of TFT is generally tens or hundreds of xcexcm or less, the single crystal silicon region provided by this method can be sufficiently used to fabricate a semiconductor device. The device fabricated by this method has significantly improved characteristics as compared to the semiconductor device including conventional poly-crystal silicon layer.
FIG. 5a illustrates a conventional technique for forming the active layer of a thin film transistor with poly-crystal silicon layer by the MILC method and FIG. 5b illustrates a state that the channel region and its peripheral regions were crystallized by the crystallization method of FIG. 5a. As illustrated in FIG. 5a, an active layer 50 is formed of amorphous silicon on a substrate 100. A metal layer for inducing MIC of the amorphous silicon active layer is deposited on portions of the source region 51 and drain region 52 of the active layer. The MIC source metal is not deposited in the channel region beneath the gate electrode 53. The MIC source metal is not deposited on the portions of the source and drain regions which are adjacent to the gate electrode 53 to form metal-offset regions 54. When thermal treatment is performed on the active layer, the crystallization propagates from the source and the drain regions 51, 52 covered with the MIC source metal towards the channel region. Thus, the entire amorphous silicon layer in the channel region and the metal-offset region 54 is crystallized as shown in FIG. 5b. FIG. 5b is a schematic diagram illustrating the crystal structure formed in the metal offset region 54 and the channel region by the crystallization process illustrated in FIG. 5a. Referring to FIG. 5b, several silicon crystals are formed on both sides of the channel region, and a MILC boundary 55, at which the MILC poly-crystal silicon regions grown from both sides of the channel region meet with each other, is formed at the center portion of the channel region. The poly-crystal silicon produced by the MILC has inferior electrical characteristics such as electron mobility as compared to those of single crystalline silicon. Particularly, the silicide the MIC source metal such as Ni, which induced the MILC in the MILC regions, is accumulated at the MILC boundary 55, and it deteriorates the electrical characteristics such as leakage current and the electron mobility of the channel region.
The object of the present invention is to provide a method for fabricating a silicon active layer and a thin film transistor by utilizing the above-described crystal filtering technique to overcome the above-mention problems of the conventional poly-crystal TFT. In order to achieve these objects, the present invention provide a method for crystallizing a silicon active layer of a thin film transistor comprising the steps of: (a) forming an amorphous silicon layer on a substrate; (b) forming a crystallization source region including MIC source metal, an active layer region and a filtering channel connecting the crystallization source region and the active layer region by patterning the amorphous silicon layer; and (c) crystallizing the crystallization source region and the active layer region by performing thermal treatment of the patterned amorphous silicon layer.
According to another aspect of the present invention, the present invention provides a method for fabricating a thin film transistor including a crystallized silicon active layer comprising the steps of: (a) forming an amorphous silicon layer on a substrate; (b) forming a crystallization source region including MIC source metal, an active layer region and a filtering channel connecting the crystallization source region and the active layer region by patterning the amorphous silicon layer; (c) crystallizing the crystallization source region and the active layer region by performing thermal treatment of the patterned amorphous silicon layer; (d) forming a gate insulating layer and a gate electrode on the active layer region; (e) doping impurity into the active layer region; (f) forming a contact insulating layer at least on the active layer region and at least one contact hole in the contact insulating layer; and (g) forming at least one contact electrode being electrically connected to the active layer region through said contact hole.
Referring to accompanied drawings, preferred embodiments of the crystal filtering technique and the method for fabricating a TFT utilizing the crystal filtering technique are described in detail below.